The present invention generally relates to cathode ray tube controllers, and more particularly to a cathode ray tube controller which successively reads out from a memory image data amounting to one picture, and converts the image date into a video signal which is supplied to a cathode ray tube so as to display the picture on the cathode ray tube.
Generally, in an image display system, image data amounting to one picture is stored in a random access memory (RAM), and the stored image data are successively read out from the RAM depending on horizontal and vertical scans of the cathode ray tube (CRT). The image data read out from the RAM are converted into a video signal which is supplied to the CRT so as to display the picture thereon.
In such an image display system, a CRT controller is provided to control the write and read operations of the RAM. The CRT controller carries out a control so that the image data for display (hereinafter simply referred to as the displaying image data) are read out from the RAM and other processes such as rewriting of data in the RAM are carried out by a central processing unit (CPU). As a result, it is possible to rewrite the displaying image data at a high speed.
In an example of the conventional image display system, a CPU reads and writes image data from and into a RAM by making access to the RAM at an address which is supplied from the CPU to the RAM via a multiplexer. A CRT controller makes access to the RAM so as to read out displaying image data from the RAM, and the read out image data are supplied to a video signal generating circuit. The multiplexer carries out an address multiplexing so that only one of the CPU and the CRT controller makes access to the RAM at one time. The video signal generating circuit converts the read out image data into primary color signals of red, green and blue responsive to a synchronizing signal from the CRT controller. The primary color signals are supplied to a CRT and a picture described by the read out image data is displayed on the CRT.
Even within a horizontal scanning period, there exists a non-access interval in which the CRT controller does not make access to the RAM, but this non-access interval is considerably short compared to a horizontal scanning period. For this reason, even if a control signal indicating a start of this non-access interval is supplied from the CRT controller to the CPU, it takes time for the CPU to actually receive the control signal and switch the multiplexer so as to make access to the RAM. Therefore, it is impossible to make access to the RAM within the non-access interval.
Accordingly, even when an access request for making access to the RAM is generated in the CPU, the CPU must wait until the horizontal or vertical blanking period is reached before the access to the RAM may be made. Thus, there are problems in that the processing efficiency of the CPU is poor and the access speed to the RAM is slow.
On the other hand, in a character and pattern telephone access information network (CAPTAIN) system, for example, the image data are transmitted to the CPU irrespective of the scanning period and the blanking period. Hence, even within a horizontal scanning period, the CPU must make access to the RAM and carry out operations such as writing the image data into the RAM. As a result, there is a problem in that the conventional CRT controller cannot cope with such operations.
Furthermore, there are cases where the color of the displayed picture is changed into a predetermined color, such as the case where the displayed picture is changed to an all white picture. In this case, the CPU makes access to the RAM and initializes the RAM by rewriting all of the image data into white image data. The RAM is normally initialized within the vertical blanking period, but since the CPU rewrites all of the image data in the RAM during this initializing period, the CPU cannot carry out other processes during this initializing period. Therefore, there is a problem in that the processing efficiency of the CPU is poor.